DLI Scheme: Decoding India’s Chip Design Incentives for UPSC

Context

The Ministry of Electronics and Information Technology (MeitY) is driving India's semiconductor ambitions through the Design Linked Incentive (DLI) Scheme. Recognizing that chip design contributes up to 50% of the total value addition in the semiconductor value chain, the scheme focuses on nurturing a domestic "fabless" ecosystem to ensure technological leadership and strategic autonomy.

Strategic Importance of Fabless Design

In the semiconductor industry, "fabless" companies design chips but outsource their physical manufacturing (fabrication).

• Value Driver: Design and Intellectual Property (IP) contribute disproportionately to the economic value of a product compared to mere assembly or manufacturing.
• Strategic Autonomy: Without local design capability, a nation remains dependent on imported core technologies even if physical manufacturing happens locally.
• Economic Impact: Chip design accounts for 20–50% of the Bill of Materials (BOM) cost and 30–35% of global semiconductor sales.

What is the Design Linked Incentive (DLI) Scheme?

The DLI Scheme is an instrument under the Semicon India Programme to catalyze a self-reliant chip design ecosystem.

• Nodal Agency: Centre for Development of Advanced Computing (C-DAC).
• Target Beneficiaries: Domestic Startups and MSMEs.
• Eligibility:
• MSMEs: As per the June 2020 notification.
• Startups: As per the DPIIT 2019 notification.
• Domestic Companies: Owned by resident Indian citizens.

Components of the DLI Scheme

The scheme provides two main types of support:

1. Financial Incentives

• Product Design Linked Incentive: Reimbursement of up to 50% of eligible expenditure, capped at ₹15 crore per application.
• Deployment Linked Incentive: Incentives of 6% to 4% of net sales turnover over five years, capped at ₹30 crore per application. Minimum cumulative sales of ₹1 crore (startups/MSMEs) or ₹5 crore (others) is required.

2. Design Infrastructure Support

Implemented through the ChipIN Centre at C-DAC, providing:

• National EDA Tool Grid: Remote access to advanced Electronic Design Automation (EDA) tools.
• IP Core Repository: Access to libraries for System-on-Chip (SoC) design.
• Prototyping & Validation: Fiscal support for fabricating designs in Multi-Project Wafer (MPW) manner and post-silicon validation.

Key Outcomes and Success Stories

As of early 2026, the scheme has shown significant traction:

• Footprint: 95 startups supported; 24 specific chip-design projects sanctioned.
• Technological Milestones: 16 tape-outs completed, 6 chips successfully fabricated, and 10 patents filed.
• Talent: Over 1,000 specialized engineers engaged.
• IP Generation: Development of 140+ reusable semiconductor IP cores.

Notable Projects:

• InCore Semiconductors: Developing the indigenous Dolomite RISC-V processor for edge-AI applications.
• Netrasemi: Successfully taped out India’s first indigenously designed AI SoC in a 12 nm process for surveillance.
• Aheesa Digital Innovations: Developing the Vihaan fiber-broadband solution based on the VEGA processor.
• Vervesemi: Focus on motor-control chips for consumer appliances (fans, drones) and e-scooters.

Significance for India

• Reducing Import Dependence: Lowers the reliance on imported semiconductor IPs and chips.
• Supply Chain Resilience: Protects against global disruptions by diversifying the manufacturing and design base.
• Security: Ensures assured access to critical technologies for sensitive sectors like Defence, Telecom, and Space.
• Ecosystem Growth: Translates deep-tech innovation into market-ready products, leveraging 3× private investment for every rupee of government support.